Emulation Engineer

About Etched Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Key responsibilities - Oversee SoC bring-up on emulation platforms; diagnose and resolve failing SoC/processor tests. - Develop and maintain automated build and regression flows to accelerate pre-silicon validation and software development. - Provide support across emulation environments using advanced techniques including C/C++ DPI transactors, coverage analysis, and in-circuit emulation for high-speed protocols. - Collaborate closely with Design, DV, Silicon Validation, Performance, and Software teams, and partner with leading emulation vendors to enhance platform capabilities and resolve complex issues. - Develop high-performance infrastructure to capture debugging signals and surface actionable insights for users. - Implement hybrid emulation environments using custom DPI-based streaming transactors. - Create highly configurable chip-to-chip network models using emulation-efficient primitives. - Build and maintain CI pipelines and git-based workflows for emulation build reproducibility and regression tracking. You may be a good fit if you have - Hands-on experience with emulation platforms such as Palladium, Protium, Veloce, ZeBu, or HAPS, covering design bring-up, build flows, debugging, and performance tuning. - Strong C/C++ and Linux system development skills. Proficiency with SystemVerilog and Verilog, including DPI-based interfaces. - Experience with git-based development workflows and scripting (Python) for automation and flow development. Strong candidates may also have experience with - Experience with UVM verification environments. - Background in design verification, DFT, and testbench modeling. - Familiarity with waveform debug tools such as Verdi or SimVision. - Experience with SLURM or similar job schedulers for managing large emulation workloads. - Familiarity with CI/CD tooling (e.g., Jenkins, GitHub Actions) applied to hardware or pre-silicon validation flows. Benefits - Medical, dental, and vision packages with generous premium coverage - $500 per month credit for waiving medical benefits - Housing subsidy of $2k per month for those living within walking distance of the office - Relocation support for those moving to San Jose (Santana Row) - Various wellness benefits covering fitness, mental health, and more - Daily lunch and dinner in our office - Unlimited compute budget subject to ROI justification Compensation Range - $150,000 - $275,000 How we’re different Etched believes in the Bitter Lesson http://www.incompleteideas.net/IncIdeas/BitterLesson.html. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.   We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.